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AMD Zen 2’s chiplet design is a short-term fix that’s “going to run out pretty quick”

AMD says it needs to use "every trick in the book" and that means 3D stacking is a must for next-gen architectures

AMD Zen 2 chiplet design for Rome processor

At a high-performance computing event this month AMD has given a little more detail about the 3D chip-stacking techniques it’s looking at to mitigate the slowing of Moore’s Law. The multi-chip, or chiplet architecture that’s propping up the AMD Ryzen 3000 processors launching this year looks to only be a step on the road towards fully 3D stacked, heterogeneous processor designs.

With the performance benefits of process node shrinks weakening with every new lithography AMD is keenly looking for ways to keep its products moving forward. While the new Zen 2 chiplet design is an important technique for increasing the amount of silicon in a single socket, it’s a trick that’s going to lose its lustre fast.

“That technique of putting more and dies is going to run out pretty quick,” says Forrest Norrod, senior vice president and GM of AMD’s datacentre group, “because there’s a physical limit to how many die you can put into a given socket area. We’re already at the point where today’s CPUs, the packages, are pretty darned close to the size of the original iPhone. They’re huge. You can’t get any more area in two dimensions, so what do you have to do? You go up.”

Norrod was speaking at the Rice Oil and Gas HPC conference (via Tom’s Hardware) and made the point that even combining chiplet design with true 3D stacking isn’t enough to keep things moving ever forward in terms of performance gains. AMD sees the need to pair such techniques with scalable interconnects, new memory architectures, and new software frameworks too.

“The only way to do it is by using every way,” says Norrod, “every trick in the book.”

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The problem is that all the traditional methods we’ve been seeing used to continue on the Moore’s Law trajectory are starting to run dry. And the biggest tricks have been either increased clock frequency or increased density scaling.

Graph plotting process frequency scaling

“You saw a continuous improvement in clock frequency of digital systems for many, many years” explains Norrod. “The dirty little secret in the industry though, over the last ten years that has stopped, and may now be regressing.

“We have really been peaked at a maximum frequency, it’s somewhere between 3 and 4GHz for at least datacentre classed systems. The intractable combination of reliability constraints, power constraints, various scaling constraints on resistivity of metal, means that as we continually shrink our processes now we don’t get any more frequency. Really with this next node, without doing extraordinary things, we get less frequency.”

So if frequency gains are slowing down you utilise the shrinking transistors to squeeze ever more logic into the same space.

Graph plotting process node scaling

“It’s alright, it’s cool, density will save us,” says Norrod. “We will just throw more transistors at the problem and that’s what we’ve done for the last ten years… we’re throwing more and more cores, cache, etc. at the problem and we’ve got through the last decade by throwing a lot more transistors into each piece of silicon. The bad news is that game is slowing down as well… It’s not quite done yet, but we can see it on the horizon.”

So, as every would-be town planner knows, it’s time to start building upwards. And, while we’ve already got GPUs with high-bandwidth memory strapped to the same die, the future is about true 3D stacking. AMD isn’t alone in thinking this; Intel announced its own Foveros technology last year, being introduced into the Intel Lakefield CPUs launching this year.

That’s a chiplet design combined with stacked CPU/GPU and I/O layers, with a couple of DRAM strata topping it off. And that’s the direction AMD is looking to go in too.

“We’re going to move to true 3D stacking,” explains Norrod, “where you do put SRAM and DRAM on top of silicon computing components to give even more bandwidth and continue unlocking more and more performance.”

AMD multichip architectures

To start with it’s going to be most important for memory, and using the interconnects and software developments to create a coherent pool of memory that can be accessed by CPU and GPU as one.

That’s not going to appear in next year’s Zen 3, expected in 2020, that’s looking like it’ll be more of a half-generation update than a full redesign of the Zen 2 chiplet architecture.

Though maybe Zen 3 will arrive with heterogeneous chiplets, with CPU and GPU chiplets intermingling in different chiplets on the same package. That would give us a whole new kind of APU.

But it’s quite possible that Zen 4 will be the next generation architecture to see a true 3D stacked processor arriving in AMD form for the first time, and quite possibly with a whole new socket design to support it.