The future of Intel CPU design is a Frankenstein’s monster of an architecture | PCGamesN

The future of Intel CPU design is a Frankenstein’s monster of an architecture

Intel Heterogeneous CPU design

Intel have just announced the future of their CPU design will be built around the new embedded multi-die interconnect bridge (EMIB), a technology which will allow chips from different generations to be stitched into the same package. This may also be how AMD GPU silicon finds its way into Intel processors.

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A report on PC World from Intel’s technology and manufacturing day in San Francisco highlighted the new heterogeneous CPU design made possible by this new EMIB interface. The new bridge promises a huge amount of bandwidth to allow different chips to be able to talk to each other at speeds in the “multi hundreds of gigabytes,” according to Intel’s Murthy Renduchintala.

This new design will mean 22nm, 14nm and 10nm silicon could all sit within the same processor, but with the new interconnect able to cut the traditionally prohibitive latency of multichip packages by up to four times.

Intel's Murthy Renduchintala

The idea is for Intel to be able to rapidly move from generation to generation without necessarily having to completely overhaul the entire architecture. Non-performance related components could then remain on the previous generation’s lithography while only the high-performance parts of a CPU design would need to be on the latest, lower-yield process node.

This sounds an awful lot like a patent application Intel filed back in 2014, which recently came to light via Seeking Alpha. The patent covers the method for stacking multiple cores in a single package and covers the potential cost reductions of going for smaller 3D stacked designs over larger monolithic layouts, and how it will at least halve the time to market of Intel’s complex server CPUs. It will potentially also allow Intel to quickly ramp up the core-count of their client processors too.

Intel's stacked CPU design

The new EMIB though will take the place of a silicon interposer and through silicon vias (TSVs) and provide the bandwidth to make such designs possible from a high-performance point of view.

It also paves the way for different silicon designs to talk to each other at speeds necessary for them to make a viable alternative to large monolithic designs. And that means, if the rumours of Intel licensing actual AMD GPU silicon and not just IP are true, this could be how they can jam a Radeon chip into an Intel package.

“This Lego-like ability to incorporate big and small cores, graphics, FPGAs and custom accelerators,” says the patent, ”provides an unprecedented flexibility to customize server processors at assembly time for specific OEM workloads and compute requirements.”

Intel haven’t made any commitments as to when this ‘mix and match’ heterogeneous design will enter production, but Renduchintala is said to have mentioned at yesterday's event it will play a key part in near-term Intel products.

Intel Cannonlake cores

And with the patent application detailing the use of CNL (Cannonlake) cores in its design we could be looking at the method for getting the upcoming 10nm mobile design into larger, higher-performance processors.

Intel 10nm FinFETS

Cannonlake’s 10mn design is only set to arrive at the turn of the year in low-power mobile form, presumably because of low yields of the early lithography. By using this heterogeneous design Intel could offset the lower yields of the early 10nm node and still make high-performance Cannonlake CPUs around the 10nm core later in 2018.

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