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Toshiba’s 5-bit PLC SSDs will be slow and fail quicker, but should improve TLC drives

Toshiba SSD memory

Toshiba is in the process of planning a new level of SSD Flash memory that has lower endurance and slower performance. If that sounds counter-intuitive it’s because I’ve deliberately left out the only possible reason for its existence to make it seem more absurd that it really is. And the only possible reason is… higher storage density.

The chase for SSDs with the same sort of storage density, and therefore getting on towards the same price/capacity levels, as traditional hard drives has long been the goal of many a storage and memory company. Of course performance is a big thing for the SSD world, but given that we are already well beyond what a basic SATA SSD is capable of with even the worst PCIe-based NVMe drives, more capacious drives are the next focus for a lot of folk.

To that end we’re starting to see QLC, or quad-level cell, SSDs trickling into the market, and now memory maestro, Toshiba, is researching the next step – penta-level cell. For those of you not up on your ancient Greek numerical shiz that’s a NAND Flash memory tech capable of storing five bits per cell, an improvement on the four bits of QLC and the three bits of the current TLC standard.

The news has come from the Flash Memory Summit in Santa Clara (via Tom’s Hardware) where Toshiba’s keynote delved into its future storage memory tech. Its BiCS Flash has been used in many a modern SSD, and powers some of our favourite drives, such as the WD Blue SN500 and WD Black SN750, and Tosh has waxed lyrical about the next generations of its tech.

BiCS Gen5 will launch as the de facto Toshiba NAND for PCIe 4.0 SSDs, offering 50% increase in bandwidth over the current Gen4 BiCS. Gen6 will nominally coincide with the release of the PCIe 5.0 standard and BiCS Gen7 will be targeted at PCIe 6.0, offering 33% and around 25% higher bandwidth as they go.

NAND Flash memory

But that’s just the performance side of the equation, the quest for capacity is all about squeezing more bits into each memory cell and hang the consequences. Well, attempt to mitigate the consequences anyway…

PLC, or Penta-level cell, memory is seen as the natural successor to the QLC, offering five bits per cell instead of four bits per cell. QLC is already being castigated for offering lower performance and weaker endurance – at a time where prices of superior TLC SSDs are plummeting – and PLC will naturally make both even worse even if it does offer more space.

Toshiba has spoken about some ways it’s planning to mitigate some of PLC’s issues, using a new NVMe protocol called Zoned Namespaces (ZNS) to reduce the necessity of over-provisioning on a drive, and/or DRAM cache usage, reduce write amplification, and at the same time boost throughput and reduce latency.

But PLC is also proving a pretty tricky technology to nail down too. In order to deliver five bits per memory cell PLC has to store 32 different voltage levels and the connected SSD controller has to be able to read them all back accurately for it to function. But the benefit of the effort Toshiba’s putting into PLC is that it should also feed back into TLC and QLC SSDs and provide enhanced performance for both of those existing Flash technologies too.

And, to me, that’s arguably more promising than the currently rather dubious benefits of Penta-level cell Flash.

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