The 7nm process node accounts for just 30% of AMD Navi’s performance gains | PCGamesN

The 7nm process node accounts for just 30% of AMD Navi’s performance gains

AMD RX 5700 XT GPU

Process nodes are often cited as the be all and end all of silicon performance. But there’s far more to it than that. AMD’s rolling out 7nm for the first time in the mainstream desktop space with its RX 5700-series GPUs, Navi, yet TSMC’s advance node reportedly accounts for just roughly 30% of its latest graphics cards’ performance.

AMD is introducing a brand new architecture with AMD Navi called RDNA, which leverages the Zen CPU design methodology. It’s the replacement for Graphics Core Next (GCN) that has served us well for years, but it’s time to move on, and RDNA will be utilised across AMD’s entire graphics product stack from high-end to mobile chips very soon. Both Microsoft and Sony are set to use it in their next-gen consoles, too.

The graphics architecture has largely been supercharged by performance per clock enhancements, AMD says. Those optimisations in the backend, such as the new Compute Unit design, multi-level cache hierarchy, and streamlined graphics pipeline, have proven instrumental in increasing performance – responsible for just a little under 60% of RDNA’s graphical gains over the previous generation.

The new Compute Unit is fitted with double the scalar units and schedulers, offering improved single-threaded performance and cuts to execution latency. Meanwhile the multi-level cache hierarchy reduces latency at each cache level, and improving the effective bandwidth along the way.

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You can thank the streamlined graphics pipeline for the rest. Performance per clock and less logic on chip makes for a high frequency, power efficient chip.

RDNA performance contributors

The 7nm process node is still important, however. It offers a 2.3x performance per area increase over an RX Vega 64, and there’s a major difference in size between the 14nm and 7nm chips.

As for the last 10%, that all comes down to design frequency and power improvements, such as “hyper-effective” clock gating on chip.

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